Verilog HDL Synthesis (Record no. 97149)
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| 000 -LEADER | |
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| fixed length control field | 00000nam a2200000 a 4500 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20251203110632.0 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 8178000113 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.3 |
| Item number | BHA |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Bhasker, J |
| 245 ## - TITLE STATEMENT | |
| Title | Verilog HDL Synthesis |
| Remainder of title | A Practical Premier |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | Hyderabad |
| Name of publisher, distributor, etc. | BS Publications |
| Date of publication, distribution, etc. | 1998 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xx,215p. |
| Dimensions | 24 cm. PB |
| 690 ## - LOCAL SUBJECT ADDED ENTRY--TOPICAL TERM (OCLC, RLIN) | |
| Topical term or geographic name as entry element | Verilog HDL -Hardware description language |
| 964 ## - | |
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| 997 ## - | |
| -- | 113567 LIBSC C |
| Withdrawn status | Lost status | Damaged status | Not for loan | Home library | Current library | Date acquired | Cost, normal purchase price | Total checkouts | Full call number | Barcode | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Central Library | Central Library | 21/07/2005 | 195.00 | 621.3 BHA | 113567 | Books |